Compact Implementation of ARIA on 16-Bit MSP430 and 32-Bit ARM Cortex-M3 Microcontrollers

In this paper, we propose the first ARIA block cipher on both MSP430 and Advanced RISC Machines (ARM) microcontrollers. To achieve optimized implementation target embedded processors, core operations of ARIA, such as substitute diffusion layers, are carefully re-designed for (Texas Instruments, Dallas, TX, USA) ARM Cortex-M3 microcontrollers (STMicroelectronics, Geneva, Switzerland). particular, two bytes input data in concatenated to re-construct 16-bit wise word. The word-wise operation is executed at once with instruction improve performance microcontroller. This approach also optimizes number required registers, memory accesses, half numbers rather than 8-bit word implementations. For microcontroller, 8×32 look-up table based further novel access. access finely scheduled fully utilize 3-stage pipeline architecture Furthermore, counter (CTR) mode more through pre-computation techniques electronic code book (ECB) operation. Finally, proposed implementations low-end (MSP430 Cortex-M3) achieved (209 96 128-bit security level, respectively), (241 111 192-bit (274 126 256-bit respectively). Compared previous works, running timing improved by (92.20% 10.09% (92.26% 10.87% (92.28% 10.62% ARIA–CTR 6.6% 4.0% compared ARIA–ECB microcontrollers, respectively.